Abstract: The Serial-Peripheral Interface (SPI) protocol is a very essential protocol for connecting between the peripherial devices and microprocessors. As the number of devices in the circuit increased as the advancement of IC technology. So, in order to lessen the product failure self-testability in hardware is demanded a lot in recent times. For the testing of devies we can use self-testability which is called as Built-in-self-test (BIST). BIST is an effective solution to reduce the huge circuit testing cost. This paper represents designing and implementation of SPI protocol with BIST capability over FPGA. An EEPROM and FPGA Spartan 2 are used for the communication testing where the FPGA is master and EEPROM is a Slave. The need of programming for setting up a network with two devices is no longer needed in this proposed system. To accomplish compact, stable and reliable data transmission, the SPI is designed with VHDL language and synthesized on Spartan 2 FPGA.
Keywords: Serial-Peripheral Interface; Embedded built-in-self-test architecture; Verilog HDL; FPGA