Abstract: In this paper, the efficient bus architecture AMBA AHB is defined to support most advanced bus functionalities was designed and the hardware modelling for that architecture was done using VERILOG (IEEE STD 2001) and simulated in Modelsim. The scheme involves read and write transactions, lock transactions, pipelined transactions of the standard. AMBA (Advanced Microcontroller Bus Architecture) was introduced by ARM in 1996 as registered trademark and is an open-standard communication protocol, as more IP cores are integrated into an SOC design, the communication flow between IP cores has increased drastically and the efficiency of the on-chip bus has become a dominant factor for the performance of a system. The AHB design implementation is done with one master and four slaves, according to decoding scheme master can access the bus slaves based on generated address range. One entity acts as the master of the AHB instance, and the other IPís acts as the slaves of AHB instance and only the master can present commands and is the controlling entity. The slave responds to commands presented to it, either by accepting data from the master, or by presenting data to the master. Upgradeability and Customization benefits of programmable logic can be obtained by FPGA implementation.

Keywords: AMBA-AHB, Master and Slave protocols, System-on-chip (soc), FPGA, Intellectual property.