Abstract: Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This paper uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-b, 16-b, 32-b, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and uses layout 0.18-m CMOS process technology. The proposed CSLA structure is better than the regular SQRT CSLA from the obtained results.
Keywords: Ripple Carry Adders, Binary to Excess-1 Converter, SQRT CSLA.