Abstract: Many wireless communication standards like IS-95, UMTS and WCDMA adopt root raised cosine filter as the channel filter for its ability to reduce BER by disallowing timing jitter at the sampling instant. However, different standards involve different oversampling rate and roll-off factor for the RRC filter. To support all of these standards in a single device, a reconfigurable RRC filter is needed. This has motivated us to propose a new architecture for a reconfigurable RRC filter in this paper and implement it on FPGA platform. This paper proposes new low-power, high-speed architecture and synthesized result of a multi-tap reconfigurable RRC FIR filter, one of the major components in DUC. The proposed RRC filter can support three different interpolation factors along with two different roll-off factors mostly used in the present days wireless communication standards. The design presented in this paper can be reconfigured at any time by selecting the proper value of the two parameters, interpolation control and roll-off factor control parameter. The design is fully multiplexer based, by which controllable switching activity has been made and reduction in the area has also been achieved.
Keywords: RRC FIR Interpolation Filter, Software Defined Radio, FPGA, Reconfigurable Architecture, Digital Up Converter, BCSE Algorithm.