Abstract: In high speed VLSI applications adders play important role. According to conventional studies much research is done on various parameters like delay, area, and power. Considering recent scenario optimization of all parameters is needed, this gives rise to idea of hybrid systems. Thus two new hybrid carry select adders are studied involving the Carry Select and Section Carry based Carry Lookahead sub adders. In this paper comparative study of 32bit Hybrid carry select adder is proposed involving variable input bit partitioning resulting in optimized delay. Performance of proposed designs is studied under Verilog HDL and subsequently implemented in a FPGA (Spartan-3E). The results obtained show that the carry select adder utilizing section-carry based carry lookahead logic with (8-8-8-8) input bit partitioning encounters minimum data path delay.
Keywords: Carry select adder, input partitioning, Verilog, FPGA.