Abstract: In Digital Signal Processing, the convolution and de-convolution with a very long sequence is ubiquitous in many application areas. The basic blocks in convolution and de- convolution implementation are multiplier and divider. They consume much of time. This paper presents a direct method of computing the discrete linear convolution, circular convolution and de-convolution. The approach is easy to learn because of the similarities to computing the multiplication of two numbers. The most significant aspect of the proposed method is the development of a multiplier and divider architecture based on Ancient Indian Vedic Mathematics sutras Urdhvatriyagbhyam and Nikhilam algorithm. The results show that the implementation of linear convolution and circular convolution using vedic mathematics is efficient in terms of area and speed compared to their implementation using conventional multiplier & divider architectures. The coding is done in Verilog HDL. Simulation and Synthesis are performed using Xilinx ISE design suit 14.2. Simulated results for proposed 4x4 bit Vedic convolution circuit shows a reduction in delay of 88% than the conventional method and 41% than the OLA method.
Keywords: Linear Convolution, Circular Convolution, De-convolution, Vedic Mathematics, Urdhva Triyagbhyam, Paryavartha, VerilogHDL.