Abstract: This paper proposes about new FIR filters that are implemented using multiple constant multiplications (MCM). This technique helps in reducing delay and power efficiency. It also helps to reduce area to some extent. All symmetric computations are performed by multipliers as the multipliers functions in symmetric manner. Multiple constant multiplications make use of two techniques common sub-expression (CSE) algorithm and GB algorithm technique to implement the multipliers. In this proposed system we have reduced down the use of number of adders, subtracters, shifters etc. to minimum and these are replaced by use of multipliers for increasing the efficiency of the filters. This paper also describes that the delay and power is reduced by replacing the conventional multipliers by multiple constant multiplications multipliers. Simulation is done by using Xilinx ISE tool suite 14.6 tool. The results obtained in this project are considered with respect to 8-bit inputs.
Keywords: Multiple constant multiplications (MCM), Common sub-expression algorithm (CSE), GB algorithm.