Abstract: Today most of the DSP applications are supported real time transmission method. Digital illustrations of transmission data are typically handled inside a similar methodology as text; however the method rate possesses to be overabundant faster. On account of this real time production constraint, normal processors are not acceptable for up to date day DSP systems. Some hardware economical algorithms are, therefore required for these high speed applications. These algorithms need to be enforced associate optimized in hardware therefore on modify them to handle real time data whereas maintaining associate optimum trade-off between fully totally different performance parameters (speed and power). CORDIC is one such algorithmic rule. CORDIC (Coordinate Rotation Digital Computer) could also be a hardware economical shift-and-add algorithmic rule which is able to be wont to calculate varied arithmetic functions. The algorithmic rule incorporates a really simple operation requiring exclusively shift and add operations. So, this project aims to implement a CORDIC processor with every rotation mode and vectoring mode on FPGA Virtex-5. This project focuses on reducing low power in bit-parallel unrolled CORDIC structures by modelling the shift activity and the charging/discharging capacitance among the essential path.
Keywords: FPGA, Virtex-5, sine cosine, square root function, LUT.