Abstract: Multipliers have great importance in both digital signal processors and microprocessors. So designing a reliable multiplier is the most important factor in designing a signal processor. Fast multiplication process is very important in DSPs for convolution, Fourier transforms etc. Power, speed and area are the prime design constraints of a multiplier for signal processing applications. Here a comparative analysis is made on different multiplier architectures which have been used for various signal processors. The different multipliers architectures chosen are array multiplier, a column bypass multiplier, row bypass multiplier, Vedic multiplier and Booth Wallace multiplier. The multiplier architectures simulated using tanner EDA tool and the results are compared in terms of delay, power consumption and area.
Keywords: Multipliers, power consumption, delay, area