Abstract: A new low power weighted pseudorandom test pattern generator using weighted test-enable signals is proposed using a new clock disabling scheme .It supports both pseudorandom testing and deterministic BIST. To implement the low power BIST scheme, a design-for-testability (DFT) architecture is presented. During the pseudorandom testing phase, an LP weighted random test pattern generation scheme is used by disabling a part of scan chains.A novel low-power bit-swapping LFSR (BS-LFSR) is used to minimize the transistions, while keeping the randomness almost similar. The BS-LFSR is combined with a scan-chain-ordering algorithm that orders the cells in a way that reduces the average and peak power (scan and capture) in the test cycles (or) while scanning out a response to a signature analyzer. These techniques have a substantial effect on average and peak power compared to the existing approach.
Keywords: Built-In Self-Test, Scan chain, Linear Feedback Shift Register, Bit Swapping, Cell Ordering and Design-for-Testability.