<P align="justify"><B>Abstract:</B>

As signal-processing circuits become more complex, it is common to find several filters or FFTs operating in parallel. Soft errors pose a reliability threat to modern electronic circuits. This makes protection against soft errors a requirement for many applications. Communications and signal processing systems are no exceptions to this trend. For some usage, an attractive choice is to use Algorithmic-Based Fault Tolerance (ABFT) techniques that try to effort the algorithmic properties to detect and correct errors. One example is Fast Fourier transforms (FFTs) that are a key building block in many systems. Several protection schemes have been proposed to detect and correct errors in FFTs. Among those, perhaps the use of the Parseval or sum of squares check is the most widely known. Recently, a technique that exploits this fact to implement fault tolerance on parallel filters has been proposed. In this brief, this technique is first applied to protect FFTs. With the help of error correction codes and parseval checks are arranged and checked to protect FFTs. The results show that the proposed schemes can further reduce the implementation cost of protection complexity of communications and signal processing circuits increases every year. In this technique, the idea is that each filter can be the equipment of a bit in an ECC and parity check bits can be computed using addition. This technology is used for operation, in which the output of the sum of several input is the sum of the individual outputs. This is true for any linear operations as Discrete Fourier transform (DFT).This can be simulated with the help of simulation tools like Xilinx and ModelSim.

 

 

 

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<P><B>Keywords:</B>

DFT, FFT, ECC, Parity SOS, Parseval check, Soft Errors.

 

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