Abstract: VLSI Chips have some complexity. The increasing level of integration results in small features size, and high proximity of functional units. This leads the system highly susceptible to external faults which turns the need for testing. This paper proposes a Test Pattern Generator for Built-In Self-Test. Our method generates multiple single input change vectors in a pattern, i.e., each vector applied to a scan chain is a SIC vector. A Reconfigurable Johnson Counter and a Scalable SIC counter are developed to generate a class of minimum transition sequences. The proposed TPG is flexible to both the test-per-clock and the test-per-scan schemes. A theory is also developed to represent and analyse the sequences and to extract a class of MSIC sequences. . Analysis results show that the produced MSIC sequences have the favourable features of uniform distribution and low input transition density. It also achieves the system fault coverage without increasing the test length.
Keywords: SIC, TPG, MSIC.