Abstract: Reversible computing has been gaining a great deal of attention from researchers because of its low power consumption. A good amount of research work has been carried out in the area of reversible combinational logic as well as sequential design of reversible circuits. In this paper we proposed efficient designs for both the asynchronous and synchronous counter circuits that are optimized in terms of quantum cost, delay and the number of garbage outputs.

Keywords: Reversible Logic, Delay, Garbage Output, Flip-Flop, Quantum Cost.