Abstract: In this paper we have shown the design and implementation of multiplier in which carry save adder is used as an adder block for the addition of partial products of both multiplier and multiplicand as 64 bits and the product size is of 128 bit. Multiplication is the fundamental arithmetic operation that plays a critical role in several processors and digital signal processing systems. Digital signal processing systems need multiplication algorithms to implement DSP algorithms such as filtering where the multiplication algorithm is directly within the critical path. The Finite Impulse Response (FIR) filter is a digital filter widely used in Digital Signal Processing applications in various fields. The implementation of an FIR requires three basic building blocks i.e. Multiplication, Addition, Unit delay. In a DSP system the multiplier must be fast and must have sufficient precision (bit width) to support the desired application. A high quality filter will in general require more multiplications than one of lesser quality, so throughput suffers if the multiplier is not fast. Hence 64 bit multiplier with carry save adder is designed and the same block which is of 8 bit is implemented in FIR (8-tap) filter. A comparison between array multiplier and multiplier with carry save adder is shown and the proposed technique is efficient in terms of power. A comparison between FIR filter with array multiplier block and FIR filter with multiplier with carry save adder block is shown and the proposed technique is efficient in terms of power and speed. The code is written in Verilog and the simulation and synthesis is carried out in Cadence Encounter tool.
Keywords: Cadence Encounter, Verilog, Array Multiplier, Multiplier with Carry Save Adder, FIR Filter with Array Multiplier block, FIR Filter with Multiplier with Carry Save Adder block.