Abstract: This project describes Design and Implementation of DDR3 Controller with AXI Compliancy. It explains the architecture of the DDR3 controller along with the detailed design and operation of its individual sub blocks. It also discusses the advantage of DDR3 memories over DDR2 memories and the AXI protocol operation. The AXI DDR3 Controller provides access to DDR3 memory. It accepts the Read / Write commands from AXI and converts it into DDR3 access. While doing this it combines AXI burst transactions into single DDR access where ever possible to achieve the best possible performance from DDR3 memory subsystem.
Keywords: Verilog HDL, Xilinx ISE, Model Sim Simulator, AXI, DDR3 Memory, DDR3 Controller, FIFO.