Abstract: High speed addition and multiplication has always been a major requirement of high processing unit. The speed of addition and multiplication operations depends on speed of adders used in the design. Ripple carry adders (RCA) has better area utilization but has more delay, whereas the Carry Select Adder(CSLA) use two RCAs and increases the speed. The regular Carry Select Adder consists of dual ripple carry adders and multiplexers. The carry out calculated from the last stage i.e. least significant bit stage is used to select the actual calculated values of the output carry and sum of the next bit stages. The main disadvantage of regular CSLA is the large area due to multiple pairs of RCA and more power consumption. The modified CSLA using Common Boolean Logic (CBL) structure replaces the multiple use of RCA by using one inverter (INV) and OR gate. By using multiplexers, we can select the correct output result according to the logic state of carry-in signal from the previous bit stage. This structure consumes less area, delay and power. In this paper we have implemented two architectures of CSLA and simulated in cadence Spectre and compared the parameters like delay, area and power. The layout of CSLA using CBL logic is implemented using Cadence Layout editor-virtuoso with Standard cell library and grid routing techniques.
Keywords: Carry select adder, standard cell library, grid based routing.