Abstract: A Cyclic Redundancy Check (CRC) is the remainder or residue of binary division of a potentially long message, by a CRC polynomial. This technique is ubiquitously employed in communication and storage applications due to its effectiveness at detecting errors and malicious tampering. The hardware implementation of a bit-wise CRC is a simple linear feedback shift register. This means that ‘n’ clock cycles will be required to calculate the CRC values for an n-bit data stream. This project primarily focuses on error detection in the Ethernet applications. This paper presents implementation of parallel Cyclic Redundancy Check (CRC) based upon DSP algorithms of pipelining, retiming and unfolding. The architectures are first pipelined to reduce the iteration bond by using novel look-ahead techniques and then unfolded and retimed to design high speed parallel circuits. The methodology to be employed with VHDL, Xilinx ISE for simulation and test-bench verification.
Keywords: Cyclic Redundancy Check (CRC), Parallel Pipelining, LFSR, VHDL code.