Abstract: Fast Fourier Transform (FFT) algorithm is extensively used in numerous signal processing and communication systems. Due to its rigorous computational requirements, it occupies large area and consumes high power if implemented in hardware. By using the FFT concepts we are certainly in emerging efficient architectures for wireless networks which are common in universally now-a-days. The SDC processing engine (PE) is proposed to achieve 100% hardware resource utilization by sharing the common arithmetic resource in the time-multiplexed approach, including both adders and multipliers.

Keywords: FFT, Pipelined Architecture, SDF-SDC.