Abstract: Power consumption is most important parameter for concern in CMOS technology. For past several years, technology scaling is the most important procedure for the improvement of the performance of circuit in terms of the power, speed etc. In this paper, design and analysis of double tail comparator with sleep transistor is done in terms of power, delay and noise. Comparator is the very important circuit in the digital design and the performance of comparator is defined in terms of power and speed, which is the most important factor in attaining the complete performance of ADCs. Several ADCs require small delay, Low power comparators with small die size. It is observed that in the proposed comparator power, delay and pdp is reduced having values of 169.9e-9 watts, 319.7ps and 54.25e-16 respectively.
Keywords: ADC, Double-tail Comparator, Dynamic Comparator, Low power design.