Abstract: Content Addressable Memory is a storage unit built on hardware. It is majorly used in internet routers to access fast look up tables. Available techniques to build CAM are power inefficient as CAM implements parallel comparison unit in its design. This project has implemented the content addressable memory using Master-Slave Match Line architecture. In the Master –Slave configuration, the CAM word is divided into number of segments. Each segment is provided with an additional slave match lines along with one Master Match Line. This configuration reduces the voltage swing across the Match Line (ML). By reducing the voltage swing, the power consumption across the Match Line is reduced. Finally, 128x8 CAM memory is implemented. The CAM array is tested for different possible cases. When the data is given to the CAM array, it is searched simultaneously in the entire memory. The 128X8 CAM array is tested at both lower frequencies and higher frequencies.
Keywords: CAM; MSML design; 4T CAM; Match Delay; HSPICE.