Abstract: Multipliers play the key role in the design of high speed arithmetic logic units, Internet of things and digital signal processing applications. Multipliers using Vedic mathematics with different adders improve the performance of the multiplier. Performance parameters like less gate count and high speed are obtained in Vedic multipliers by using different techniques like Carry select adder, Carry save adder and Binary to Excess-1 converter. Vedic multiplier using koggestone adder gives better performance in terms of area, when compared to Vedic multiplier using CSLA. The multiplier is implemented on Spartan 3E FPGA and simulation is performed using verilog HDL.
Keywords: Binary to Excess -1 converter (BEC), Carry save adder (CSA), Carry Select adder (CSLA), Koggstone adders (KSA), Vedic multiplier.