Abstract: With the advancement of Very-large-scale integration (VLSI) technology, research is going on to build more complex and robust computing systems in a single silicon chip. Interconnection requirements increase with a rapid pace with the increase of the number of components that appear on the chip thereby posing a limitation on overall on performance. Keeping this in mind we try to propose a Network on chip. The idea of a Network-on-Chip (NoC) borrows networking theory from the computer networking domain and considers each intellectual property (IP) core as a single node. In each node, a high-speed router connects with other routers of neighboring nodes. In a nutshell, the tradeoff between performance, area, and power is significant while designing routers of Network on chip. According to literature survey, the router architecture always contains buffers on the input ports. The buffer scheme is used to store packets; these packets must wait for the output resource due to contention with other packets. These designs have been widely adopted due to their improved performance. Finally, we propose a smart routing with low power, low area and improved performance. In our design Loop Back module is designed as old one, FSM is removed ,Routing Error detection , Logic, centralized Journal of data Packet are removed as our loop back module itself does the same functionality ,Ordinary Buffers are removed , instead of FIFO is used to achieve better performance.
Keywords: Hamming code, Loop Back Module, FIFO, Adaptive algorithm, dynamic reconfiguration, network-on-chip (NoC), reliability, performance, area, power, latency.