Abstract: Metastability occurs when signals are transferred between asynchronous clock domains. In today’s modern world where everything is digitized and miniaturized we need small and stable digital system for years. The circuit failure largely depends upon metastable state in digital circuits. This can be avoided by using synchronizer. The goal of the proposed work is to design a synchronizer with both CNTFET and MOSFET technology and simulate in HSPICE with 32nm scale. This paper presents how the metastability response in terms of MTBF, Noise margin, power, Delay and Power Delay Product (PDP) parameters are better in CNTFET based synchronizer as compare to MOSFET. The simulation results show that circuits designed using CNTFETs have a high robustness to voltage and temperature variations as compared to MOSFET based circuits. Also due to variation in voltage and temperature in CNTFET give no or very less variation in PDP. This paper will confirm that CNTFET technology is a viable solution to replace conventional MOSFET technology and it turns out to be an effective choice of future technology if manufacturability issues such as controllability of metallic/semiconducting property and metallic contacts are taken care of.
Keywords: CNTFET, MTBF, Sequential Circuits, MOSFET, PDP, Noise Margin