Abstract: The Urdhva- Tiryagbhyam Sutra of Vedic mathematics and we have designed multiplier based on the sutra. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras which are discovered by Sri Bharti Krishna Tirthaji. We implement the basic building block: 16 x 16 Vedic multiplier based on Urdhva- Tiryagbhyam Sutra. This Vedic multiplier is coded in VHDL and synthesized and simulated by using Xilinx ISE 13.2. Further the design of array multiplier in VHDL is compared with proposed multiplier in terms of speed and memory. With the advent of new technology in the domain of VLSI, communication and signal processing, there is an ever going demand for the high speed processing and low area design. In this paper, introduces modified compressor based multiplier architecture. This modified structure uses the 4:2 compressor and 7:2 compressor architectures. In addition to that it uses Vedic mathematics to get a high speed multiplication operation and low area design. The design and experiments carried were carried out on a Xilinx Spartan 3E series of FPGA and discussed about the results of area and speed.
Keywords: High speed multiplier, 4:2 compressor, 7:2 compressor, modified architecture, vedic mathematics.