Abstract: Digital multipliers are one of the most critical arithmetic functional units. The overall performance of this system depends on the throughput of the multiplier. Meanwhile, the NBTI effect occurs when PMOS transistor is under negative bias (Vgs = - Vdd), increasing the threshold voltage of the PMOS transistor and reducing transistor speed. A similar phenomenon, positive bias temperature instability occurs when a PMOS transistor is under positive bias. Both temperature effects degrade transistor speed, and in the long term, the system may fail due to timing violations. Thus, it is important to design reliable high performance multipliers. In this paper, we propose an aging-aware multiplier design with the novel adaptive hold logic (AHL) circuit. The multiplier is able to improve higher throughput through the variable latency and can adjust the AHL circuits to mitigate performance degradation that is due to the aging effect. The proposed design can be allied to the column bypass multiplier.

Keywords: Adaptive hold logic (AHL), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), reliable multiplier, variable latency.