Abstract: In Digital Wireless Communication application, the design of Low Power and High Speed Analog to Digital Converter (ADC) is the nee d-of- the -day. This paper explores the design of low power and high s pee d comparator us e d in all available ADC architectures. The proposed architecture includes two stage CMOS Operational Amplifier (Op-Amp) circuit. The comparator described here is designed and implemented with 0.18µm technology operate d on 1Volt power supply using Cadence Virtuoso Tool. The functional verification of the comparator is carried out which in turn consumes 0.953 µW of power with propagation delay(s pee d) of 1.561ns. The overall improvement in the results in accordance with the literature is the s cope of this paper.
Keywords: Comparator, Cadence tool, Low power, High Speed, ADC, CMOS.