**Abstract:**
Power is one of the most important design parameter after speed, in integrated circuit. One of the basic fundamental component in such circuit is adder and subtractor. In order to optimize such circuits there is need of designing efficient and low power fundamental blocks.As per the Launder’s principle, KTln2 heat is dissipated if there is any loss in bit. Excess-3 code is one of the sequential code used widely in digital circuits for performing arithmetic operations. Since conventional excess-3 adder and excess-3subtractor both circuits designed in irreversible logic observe large amount of leakage power. By keeping this as main point, this paper explains the process of designing 4-bit excess-3 adder and subtactor in 90nm technology and also worked to combine both individual circuit to design as a single circuit where it can perform addition and subtraction on excess-3 coded bits simultaneously. This paper also gives mathematical analysis of n-bit proposed circuit in terms of number of gates, quantum cost, garbage output, power and delay. Finally simulation results are obtained by using cadence virtuoso and observed power dissipation for proposed circuit is 171uW.In this paper detail simulation results along with the power graph submitted.

**Keywords:**
Quantum Cost (QC), Garbage Outputs (GO), Fredkin gate (F), Peres Gate (PG), Feynman gate (FG), Reversible MUX(RMUX), Reversible full adder (RFA), Reversible Parallel adder, GSR logic cell.