Abstract: Identifying the faults in the electronic circuits is a hard process. As the complexity of Very Large-Scale Integration (VLSI) is growing testing becomes complex and harder. A malfunctioning circuit is a result of design flaw, manufacturing defects or both. Testing is used as a measure to estimate the quality of design. Hence detecting a flaw more than one time has high degree of fault coverage. Earlier fault models are used to test the digital circuits at gate level or below that level. This project focus on creating a Register Transfer Level (RTL) modeling for the digital circuit and finding out the fault coverage of given test patterns. Fault models are taken based on the observed failures or by analyzing various types of faults. Fault coverage reflects the quality of test vectors with respect to the fault models. For a VLSI system consisting of different modules the overall coverage is a weighted sum of RTL module coverages. Here a device under test is created and fault modelling and simulation is done to obtain the fault coverage. Device under test taken here is an adder circuit which is used to analyze the process, where single Stuck-at-faults are introduced arbitrarily and the test process is carried out using 3- bit sequence pattern. These patterns, which are generated randomly flow through the entire circuit, and compare it with the faults that are present in the components, either at the input or output. During the comparison if the component response and the pattern response are same, then it is considered as a fault free component. If the response differs, they are considered as fault and are recorded. In this manner many patterns detect the same faults or different faults. The fault coverage is then analyzed for the circuit from the simulated result. This entire testing process is analyzed by using tools like MODELSIM & System Verilog. Analysis can be performed on other high-speed adder and multiplier circuits to get the fault coverage.
Keywords: VLSI, RTL (Register Transfer Level), DDS, Gates.