Abstract: In ac/dc Power Factor Correction (PFC) applications, wherever a good vary dc link voltage is needed, boost derived topologies are not any longer the foremost appropriate circuit topologies for universal grids. During this paper associate degree interleaved SEPIC device and SST capable of providing a good vary dc link voltage is investigated. The interleaved converter is able to process more power with reduced circuit ripples and harmonics distortion, and current stresses. Additionally, because the coupled inductors share a common magnetic core, the count of magnetic devices is kept the same as the single-phase topology. Moreover, using coupled inductors effectively solves the current sharing problems caused by the duty cycle mismatch. The SVM provides the phase of gate signals among different phases can be artificially shifted by a certain degree which would contribute to reduce the circuit harmonics as well as the current ripples. The output is optimized by BCO algorithm for better response from SST model.

Keywords: PFC (Power Factor Correction), SEPIC (Single-Ended Primary Inductor Converter), BCO (Bacterial Colony Optimization), SST (Solid state Transformer).