2D-DWT Lifting Based Implementation using VLSI for JPEG2000

Abstract: This paper proposes the design of VLSI architecture for image compression. The architecture has been simulated using behavioral VHDL. VHDL allows as much of the design as possible to be portable and flexible to other synthesis tools. To perform the process of image compression VLSI architecture is designed using lifting based discrete wavelet transform (DWT) and it is implemented in Spartan 3EDK kit. The decomposition algorithm of this transform is designed and synthesized with the VHDL language and then implemented on the FPGA Spartan 3E starter kit (XC3S500E) to check validation of results and performance of design. The VHDL model is validated through simulation using ModelSim-Altera. . The motivation in designing is to reduce its complexity, enhance its performance and to make suitable development on a reconfigurable FPGA based platform for VLSI implementation. The main feature of the lifting based DWT scheme is to break up the high pass and low pass filters into a sequence of upper and lower triangular matrices and convert the filter implementation into banded matrix multiplications [1], [2]. Such a scheme has several advantages, including “in-place” computation of the DWT, integer-to-integer wavelet transform (IWT), symmetric forward and inverse transform, etc. Traditional DWT architectures are based on convolutions. Then, the second-generation DWTs, which are based on lifting algorithms, are available. The outputs generated by the row and column processors are stored in memory modules. The memory modules are divided into multiple banks to accommodate high computational bandwidth requirements. The lifting based DWT architecture has the advantage of lower computational complexities and higher efficiencies. Through the DWT, signals can be decomposed into different sub bands with both time and frequency information. Compared with convolution-based ones; lifting-based architectures not only have lower computation complexity but also require less memory.

Keywords: Architecture, Flexible, DWT, Lifting scheme, FPGA, DWT processor