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International Journal of Advanced Research in Computer and Communication Engineering A monthly Peer-reviewed & Refereed journal
ISSN Online 2278-1021ISSN Print 2319-5940Since 2012
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← Back to VOLUME 4, ISSUE 12, DECEMBER 2015

A Review on High Speed CMOS Counter Using Altera MAX300A

Bindu Sebastian, Dr. Vineeth Valsan, Paulin John

DOI: 10.17148/IJARCCE.2015.412140

Abstract: Counters are widely used as essential building blocks for a variety of circuit operation. This paper present a high-speed wide-range parallel counter that achieves high operating frequencies through a state look-ahead methodology .It is a synchronous counter in which all modules are triggered at the same clock edge. The state look-ahead path prepares the counting path�s next counter state prior to the clock edge such that the clock edge triggers all modules simultaneously, thus propagation delay is avoided. The advantages for this counter is using only three module types it can be expanded to N-bit counter. Secondly there is no fan-in or fan-out increase. And the propagation delay can be minimized thus operating frequency can be improved.



Keywords: Counting path, state look � ahead logic, operating frequency, chip area.

How to Cite:

[1] Bindu Sebastian, Dr. Vineeth Valsan, Paulin John, “A Review on High Speed CMOS Counter Using Altera MAX300A,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE), DOI: 10.17148/IJARCCE.2015.412140