A review on implementation of data scrambler & descrambler system using VHDL

Abstract: Multimedia data security is very important for multimedia commerce on the internet and real time data multicast. An attractive solution for encrypting data with adequate message security at low cost is the use of Scrambler/Descrambler. Scramblers are essential components of physical layer system standards besides interleaved coding and modulation. Scramblers are successfully used in modern VLSI design especially those are used in data communication system either to secure data or re-code periodic sequence of binary bits stream. However, it is necessary to have a descrambler block on the receiving side while using scrambling data in the transmitting end to have the actual input sequence on the receiving end. Scrambling/ De-scrambling are an algorithm that converts an input string into a seemingly random string of the same length to avoid simultaneous bits in the long format of data. Scramblers have many uses in today's data communication protocols. However, those methods that are theoretical proposed are not feasible in the modern digital design due to many reasons such as slower data rate, dropping information, circuit hazards, uncountable delays etc. Therefore it is required for the modern digital design to have modified architecture to meet the required goal. We will propose here modified scrambler design which is perfectly suitable for any industrial design. Besides, we showed simulation result, detailed analysis and usage in digital design.

Keywords: Scrambler, Descrambler, VHDL, and FPGA.