A Robust Power Downgrading Technique using Sparse Modulo 2n+1 Adder

Abstract: A promising direction for dramatically suppressing the power utilised by a circuit is reducing the dynamic power which dominates total power dissipation. An architecture that reduces the power by separating the target design into two parts; MSP & LSP and it switches off the MSP whenever it does not affect the computation result to reduce the power consumption is proposed in the paper. It also introduces an advanced glitch-diminishing technique to remove the unwanted switching power by asserting the data signals after data transient period. The LSP section employs a sparse modulo adder constructed with a gray operator that do not require extra logic gates which reduces the carry computational complexity and minimizes the area for an enhanced quick output. MSP is a collection of an ordinary adder, latches, detection logic unit and a sign extension. The experimental data reveal that the proposed technique offer a higher operation speed with minimum power consumption of 0.173W.

Keywords: Low power design, modulo arithmetic, glitches, dynamic power, data transient period.