Adiabatic Vedic Multipler Design Using Chinese Abacus Approach

Abstract: In this paper, we discuss the implementation of Vedic multiplier with Chinese Abacus adder design, using Reversible Logic Gates. The power consumption of the Vedic multiplier is low as it generates all partial products and their sum in one step. Since high radix of Chinese Abacus adder reduces the carry propagation delay, it is observed here that the proposed design increases the speed of operation manifold. The proposed work is implemented on the Xilinx FPGA device, Spartan-3E. The results show that multiplier implemented using Chinese Abacus approach is quite efficient in terms of area, time and speed

Keywords: Vedic Multiplier, Chinese Abacus Adder, propagation delay, Reversible Logic