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International Journal of Advanced Research in Computer and Communication Engineering A monthly Peer-reviewed & Refereed journal
ISSN Online 2278-1021ISSN Print 2319-5940Since 2012
IJARCCE adheres to the suggestive parameters outlined by the University Grants Commission (UGC) for peer-reviewed journals, upholding high standards of research quality, ethical publishing, and academic excellence.
← Back to VOLUME 5, ISSUE 4, APRIL 2016

Analysis and Comparison of Various Sense Amplifier Topologies for SRAM

Vipul Bhatnagar, Sonali Shrotriya

DOI: 10.17148/IJARCCE.2016.54112

Abstract: Sense Amplifier are one of the most crucial circuits in the field of CMOS memories. Memory access time and overall memory power dissipation both are resultant by their performances. The existing Current Mode Sense Amplifier has ability to quickly to amplify a small differential signal Bit Lines (BLs) and Data Lines (DLs) to the full CMOS logic level without requiring a large input voltage swing. Here Analysis and Comparison done using 45nm CMOS technology shows Sensing Speed, Reliability, Power Consumption can be improved to a considerable extent. Power dissipation is improved.



Keywords: Current Controlled SA, Cache Memory, Low Power, Sense Amplifier.

How to Cite:

[1] Vipul Bhatnagar, Sonali Shrotriya, “Analysis and Comparison of Various Sense Amplifier Topologies for SRAM,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE), DOI: 10.17148/IJARCCE.2016.54112