Analysis and Mitigation of Flip-Flop Timing in Subthreshold Logic Design using Adaptive Feedback Equalization

Abstract: Ultralow-power subthreshold logic circuit is becoming prominent in embedded application with the limited energy budget. Minimum energy consumption of digital logic circuits can be obtained by operating in subthreshold regime. However in this regime process variation can result in up to an order of magnitude variation in ION/IOFF ratios leading to timing errors, which can have a destructive effect on functionality of subthreshold circuits. This timing error become more frequent in scaled technology node where process variation are highly prevalent. Therefore, mechanism to mitigate these timing errors while minimizing the energy consumption are not required. We propose tunable adaptive feedback equaliser circuit that can be used along with a sequential digital logic circuit to mitigate proceed variation and reduce the dominant leakage energy.

Keywords: feedback equalizer, leakage energy component, subthreshold.