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This work is licensed under a Creative Commons Attribution 4.0 International License.
Analysis of Power and Delay in a Reconfigurable Sram Array Architecture
ANARGA.S , V.J ARUL KARTHICK PG-Scholar, Electronics and communication, SNS College of technology, Coimbatore, India Assistant professor, Electronics and communication, SNS College of technology, Coimbatore, India
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Abstract: SRAM arrays generally occupy a large portion of the Socs and are also a significant source of power dissipation. The most commonly used arrays constitute the 6T SRAM cells. In order to achieve high reliability and long battery life for portable applications, the design of low power SRAM arrays are required. Thus reconfigurable SRAM arrays are constructed here and a comparison is made for the delay, power with that of the other arrays. This reconfigurable SRAM array is used as a memory element in applications such as ALU Design.
Keywords: Digital forensics, image compression, SPIHT compression, DWT coefficients.
Keywords: Digital forensics, image compression, SPIHT compression, DWT coefficients.
How to Cite:
[1] ANARGA.S , V.J ARUL KARTHICK PG-Scholar, Electronics and communication, SNS College of technology, Coimbatore, India Assistant professor, Electronics and communication, SNS College of technology, Coimbatore, India , βAnalysis of Power and Delay in a Reconfigurable Sram Array Architecture,β International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)
This work is licensed under a Creative Commons Attribution 4.0 International License.