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International Journal of Advanced Research in Computer and Communication Engineering A monthly Peer-reviewed & Refereed journal
ISSN Online 2278-1021ISSN Print 2319-5940Since 2012
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← Back to VOLUME 6, ISSUE 5, MAY 2017

Approximate Multiplier by Partial Product Preforation

Miss. Sasikala. V.P, Mr. R. Dharmalingam

DOI: 10.17148/IJARCCE.2017.6577

Abstract: Approximate computing appear as a promising solution to reduce their power dissipation. Such applications process large redundant data sets or noisy input data derived from the real world, do not have a golden result, perform statistical/probabilistic computations, and/or demand human interaction, thus their exactness is relaxed due to limited human perception. Approximate computing can be applied at both software and hardware levels. Hardware-level approximation mainly targets arithmetic units, such as adders and multipliers, widely used in portable devices to implement multimedia algorithms, e.g., image and video processing. Partial product generation, we introduce the partial product preforation method for creating approximate multipliers. Inspired from, we omit the generation of some partial products, thus reducing the number of partial products that have to be accumulated, we decrease the area, power, and depth of the accumulation tree.



Keywords: Approximate arithmetic circuits, approximate computing, approximate multiplier, error analysis, low power, Integrated synthesis environment.

How to Cite:

[1] Miss. Sasikala. V.P, Mr. R. Dharmalingam, “Approximate Multiplier by Partial Product Preforation,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE), DOI: 10.17148/IJARCCE.2017.6577