Carry Select Adder with Multi- Threshold CMOS Logic

Abstract: The focus of VLSI technology is to increase the speed by reducing the propagation delay from input to output. Carry propagation is also one of the reason for sequential generation of the sum for each bit after the arrival of the previous carry. But some of the adders like ripple carry adder which have less area, more delay and the carry select adder of less delay and more area the carry select adder circuitry is which has replaced many circuitry in different processing system to get faster application. There are two ripple carry adders in carry select logic adder to generate the sum for carry input equal to zero and carry input equal to one. Multiplexers are used to select the sum based on the previous carry being propagated to previous stages. In linear carry select adder, mismatch of speed between input and propagated signals creates delay problem which can be reduced by using the square root carry select adder. In square root carry select adder the ripple carry adder is divided into different block to the different bits to reduce the arrival time of previous carry bit. Ripple carry adder delay when large number of bits are considered for design. So replacing ripple carry adder for carry input equal to one with the binary to excess one converter, minimizes area and power but with slight increase in delay. D latch based square root ripple carry adder is used. To improve the performance of this system MTCMOS D latch is used. Keywords: SQRT CSLA, BEC, MTCMOS D LATCH.