Defect Secure Encoder and Decoder for very Small Memory Appliance

Abstract: The project consists of an efficient VLSI implementation of fault secure encoder and decoder for memory appliances. A novel and efficient VLSI architecture is proposed and implemented for the fault secure memory. The VLSI architecture has been authored in Verilog code for fault secure encoder and decoder for memory and its synthesis was done with Xilinx XST. Xilinx ISE Foundation 9.1i has been used for performing mapping, placing and routing. For behavioral simulation and place and route simulation ISE simulator has been used. The Synthesis tool was configured to optimize for area and high effort considerations. The interest of the project work is an attempt to obtain fault secure memory architecture. This fault secure memory is used in computer systems mainly servers and in memory appliances and also used in military appliances.
A new approach is introduced to design fault-secure encoder and decoder circuitry for memory designs. The key novel contribution of this proposed system is identifying and defining a new class of Error-Correcting Codes (ECC) whose redundancy makes the design of Fault-Secure Detectors (FSD) particularly simple. This project present a fault-tolerant nano scale memory architecture which tolerates transient faults both in the storage unit and in the supporting logic (i.e., encoder and decoder (corrector) circuitry).The proposed system with high fault-tolerant capability is feasible when the following two fundamental properties are satisfied.

Keywords: encoder,decodet, fault-tolerant detector, tolerentmemory,majoritylogiccorrector, synthesizing and optimizing