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This work is licensed under a Creative Commons Attribution 4.0 International License.
Design and Analysis for Low power CMOS Sram cell in 90nm technology using cadence tool
SAGAR JOSHI, SARMAN HADIA PG student, Charotar University of Science & Technology, changa, India Sarman K Hadia (Associate Professor, Electronics & Communication Department, CSPIT, Changa, CHARUSAT)
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Abstract: CMOS RAM Cell is very less power consuming and has very less read and writes time. As the technology is improving channel length of MOSFET is scaling down. In this environment stability of SRAM becomes the major concern for future technology. A SRAM cell must meet requirements for operation in submicron/nano ranges. So we have to modify conventional 6T SRAM circuit with additional circuitry and different kind of parametric analysis can be done and functionality is verified using Cadence Design Environment for 90nm technology files.
Keywords: SRAM, Cadence virtuoso, 90nm Technology.
Keywords: SRAM, Cadence virtuoso, 90nm Technology.
How to Cite:
[1] SAGAR JOSHI, SARMAN HADIA PG student, Charotar University of Science & Technology, changa, India Sarman K Hadia (Associate Professor, Electronics & Communication Department, CSPIT, Changa, CHARUSAT), βDesign and Analysis for Low power CMOS Sram cell in 90nm technology using cadence tool,β International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)
This work is licensed under a Creative Commons Attribution 4.0 International License.