Design and Implementation of FM0/Manchester Encoder using VHDL

Abstract: The dedicated short range communication (DSRC) is an important technique to push the intelligent transportation system (ITS) into our daily life. The transmitted signal is anticipated to have zero mean for vigor issue and this is also referred as dc-balance. The FM0 and Manchester codes are used to reach the dc-balance in DSRC. The FM0 encoder and Manchester encoder structures are different, so that limited to reuse the VLSI architecture for generating both the codes. In this work, the similarity oriented logic simplification (SOLS) scheme is used to conquer this limitation. The hardware utilization rate (HUR) of FM0 and Manchester encoders are raised from 57.14% to 100% with SOLS technique. The SOLS technique based FM0 and Manchester encoder structure has better performance compared with existing structure.

Keywords: The dedicated short range communication, Manchester, FM0, VLSI Design.