Design and Simulation of Multirate Filter using BFD Multiplier Architecture

Abstract: Interpolation and Decimation is very much effective in Multirate signal processing application. This paper proposes VLSI architecture polyphase decimation filter with decimation factor using BFD multiplier. High speed, area and power efficient are the main concerns in this VLSI design. The power dissipation can be reduced in polyphase decimation filter when uses with BFD multiplier which consumes low-power when compared to the conventional multiplier. The speed can be improved by using carry look ahead adder. This architecture also provides significant reduction in area (in terms of number of slices).

Keywords: Area, BFD multiplier architecture, Carry look ahead adder, Polyphase decimation filter, power dissipation, Speed.