Design of A Novel Low Power Dynamic Comparator Using 90nm CMOS Technology

Abstract: This paper describes design of a low power dynamic comparator which can be used in the implementation of high speed ADC. It uses a dual input single output differential amplifier as a latch stage instead of a back to back inverter. This design efficiently removes the noise at the input. Compare to existing comparators this proposed model has higher speed, lower power dissipation and higher immunity to noise. The schematic simulation has been done in Cadence� Virtuoso Analog Design Environment using GPDK 90nm technology. The layout has been done in Cadence� Virtuoso Layout XL Design Environment.

Keywords: CMOS, Comparator, Cadence, Latch.