Design of APD Efficient Carry Select Adder

Abstract: Many types of adders available to perform fast operation in digital signal processing. Carry Select Adder is high speed device used for the fast computation. In developing era the key contributing factors are faster arithmetic unit, low power and low area arithmetic units are needed. Binary to Excess-1 converter is used to the modified carry select adder (CSLA). In the proposed architecture scheme, some new technique used which is different from conventional approach. Using optimized logic unit efficient CSLA design is obtained. Recently proposed Binary to Excess I Converter based CSLA design involves significantly more delay and area than the recently proposed CSLA. The newly design proposed CSLA is a best platform for square-root (SQRT) CSLA.

Keywords: Adders, Carry Select Adder, Xilinx 14.5, Low power design, ALU.