Design of Digital Phase Locked Loop for Wireless Communication Receiver Application

Abstract: In this paper, Frequency modulated receiver is designed using Digital phase locked loop circuitry which consists of Booth s multiplier, Loop filter and Numerically controlled oscillator. This design is modelled in Verilog synthesis and performed place and route for design using Xilinx 13.1.In this paper, we propose a numerically controlled oscillator that can be tuned to desirable frequency according to the requirement. This design also achieves small area and small power consumption as compared to typical classical method of design.

Keywords: Digital phase locked loop, Booths multiplier, Numerically Controlled Oscillator.