Design of Low Power Double Edge Triggered Comparator For Successive Approximation Register (SAR) ADC

Abstract: High speed analog to digital converters (ADC), sense amplifiers, RFID applications, data receivers with low power and area efficient designs has appealed a wide variety of dynamic comparators. This paper presents design of low power double edge triggered comparator for successive approximation register (SAR) ADC. In this paper a low power double edge triggered comparator is designed for an area efficient and double edge triggered operation for a small delay. The proposed comparator structure consists of a separate cross coupled and input stage for enabling a fast operation over a wide range of common mode and supply voltages. The proposed method has been designed and simulated by using 130nm CMOS technology. The results indicate that in the proposed double edge triggered comparator, area and power consumption are significantly reduced and achieves the high speed of operation.

Keywords: comparator, ADC�s, double edge triggered, SAR.