Design of Reversible Logic ALU using Reversible logic gates with Low Delay Profile

Monika Rangari; Richa Saraswat; Rita Jain

doi:10.17148/IJARCCE.2015.4477

← Back to VOLUME 4, ISSUE 4, APRIL 2015

Design of Reversible Logic ALU using Reversible logic gates with Low Delay Profile

Monika Rangari, Prof. Richa Saraswat, Dr. Rita Jain

Downloads: Download PDF|DOI: 10.17148/IJARCCE.2015.4477

👁 34 views📥 0 downloads

Abstract:

Keywords:

How to Cite:

[1] Monika Rangari, Prof. Richa Saraswat, Dr. Rita Jain, “Design of Reversible Logic ALU using Reversible logic gates with Low Delay Profile,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE), DOI: 10.17148/IJARCCE.2015.4477

This work is licensed under a Creative Commons Attribution 4.0 International License.