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International Journal of Advanced Research in Computer and Communication Engineering A monthly Peer-reviewed & Refereed journal
ISSN Online 2278-1021ISSN Print 2319-5940Since 2012
IJARCCE adheres to the suggestive parameters outlined by the University Grants Commission (UGC) for peer-reviewed journals, upholding high standards of research quality, ethical publishing, and academic excellence.
← Back to VOLUME 7, ISSUE 1, JANUARY 2018

Designing and Optimizations Of Low Power Multiplexer Using CMOS Device Modeling

Mahima Singh, Dolly Gautam, Dr. S. S. Tomar

DOI: 10.17148/IJARCCE.2018.7139

Abstract: In today�s world power consumption is become major power concern in VLSI designing. Portable devices like laptops, cell phones, and computers require a circuitry that consumes less power. Also large power dissipation is directly associated with cost and complexity of the devices. High speed multiplier plays a dominant role in designing of digital circuits. The low power CMOS devices can be used in real time image, speech processing and 3D computers graphics application, mainly the fields where high speed is required.



Keywords: MUX, MTCMOS, CMOS, Low Power VLSI, Leakage current.

How to Cite:

[1] Mahima Singh, Dolly Gautam, Dr. S. S. Tomar, “Designing and Optimizations Of Low Power Multiplexer Using CMOS Device Modeling,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE), DOI: 10.17148/IJARCCE.2018.7139