Floating Point Parallel Processing Multiplier Based RISC (MIPS) Processor

Abstract: This paper proposes a design of high speed 32 bit RISC processor. The processor consists of blocks namely Instruction Fetch block, Instruction Decode block and Execution block. The ALU in the execution block comprises of a single precision floating point multiplier designed in a parallel architecture thus improving the speed and accuracy of the execution. Furthermore the power gating technique is used which switch off the power at the time when processor execution is not required. All the blocks are designed using VHDL hardware description language.

Keywords: RISC, Floating point multiplier, Power gating, VHDL.